According to a technique disclosed in Japanese Patent Laid-Open No. 2001-45378, in a pixel array in which a plurality of pixels is arrayed in a direction along the row (to be referred to as a row direction hereinafter) and a direction along the column (to be referred to as a column direction hereinafter), driving signals are supplied to respective pixels via a plurality of row control lines extending in the row direction, and signals are read out from respective pixels via a plurality of column signal lines extending in the column direction. Accumulation capacitances are connected to one end and the other end of each column signal line, respectively. When a signal is read out from either one of the two accumulation capacitances, a signal output from a pixel is accumulated in the other accumulation capacitance (see FIG. 21). Alternatively, two accumulation capacitances are parallel-connected to one end of each column signal line. When a signal is read out from either one of the two accumulation capacitances, a signal output from a pixel is accumulated in the other accumulation capacitance (see FIG. 22). According to Japanese Patent Laid-Open No. 2001-45378, the blanking period (during which no sensor output is obtained) is shortened to thereby shorten the total readout period.
According to a technique disclosed in Japanese Patent Laid-Open No. 11-150255, two accumulation capacitances and two amplifiers are alternately connected to respective column signal lines. A signal accumulated in one of the two accumulation capacitances is amplified by one of the two amplifiers, and the amplified signal is accumulated in the other accumulation capacitance. The signal accumulated in the other accumulation capacitance is amplified by the other amplifier, and read out to a subsequent output line.
The techniques disclosed in Japanese Patent Laid-Open Nos. 2001-45378 and 11-150255 do not mention in detail reference power supply electrodes in two accumulation capacitances. For example, these techniques do not describe a reference power supply pattern (ground pattern) for applying a reference power supply voltage (ground voltage).
On the contrary, the present inventor has made studies to find out the following new problem. Assume that a reference power supply voltage is applied to the reference power supply electrodes (ground electrodes) of two accumulation capacitances (holding capacitances) in accordance with one reference power supply pattern. When a signal is transferred from a pixel to one of the two accumulation capacitances, the potential of the reference power supply electrode of the accumulation capacitance may fluctuate. The fluctuations of the potential may be transferred to the reference power supply electrode of the other accumulation capacitance via one reference power supply pattern. If the potential of the reference power supply electrode of the other accumulation capacitance fluctuates, the fluctuations may be mixed as noise in a signal read out from the other accumulation capacitance.